PERF\-LISTSection: Misc. Reference Manual Pages (1)
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NAMEperf-list - List all symbolic event types
perf list [hw|sw|cache|tracepoint|event_glob]
Events can optionally have a modifer by appending a colon and one or more modifiers. Modifiers allow the user to restrict when events are counted with u for user-space, k for kernel, h for hypervisor.
The p modifier can be used for specifying how precise the instruction address should be. The p modifier is currently only implemented for Intel PEBS and can be specified multiple times: 0 - SAMPLE_IP can have arbitrary skid 1 - SAMPLE_IP must have constant skid 2 - SAMPLE_IP requested to have 0 skid 3 - SAMPLE_IP must have 0 skid
RAW HARDWARE EVENT DESCRIPTOR
Even when an event is not available in a symbolic form within perf right now, it can be encoded in a per processor specific way.
For instance For x86 CPUs NNN represents the raw register encoding with the layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developercqs Manual Volume 3B: System Programming Guide] Figure 30-1 Layout of IA32_PERFEVTSELx MSRs) or AMDcqs PerfEvtSeln (see [AMD64 Architecture Programmercqs Manual Volume 2: System Programming], Page 344, Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
If the Intel docs for a QM720 Core i7 describe an event as:
Event Umask Event Mask Num. Value Mnemonic Description Comment
A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and delivered by loop stream detector invert to count cycles
raw encoding of 0x1A8 can be used:
perf stat -e r1a8 -a sleep 1 perf record -e r1a8 ...
Without options all known events will be listed.
To limit the list use:
hw or hardware to list hardware events such as cache-misses, etc.
sw or software to list software events such as context switches, etc.
cache or hwcache to list hardware cache events such as L1-dcache-loads, etc.
tracepoint to list all tracepoint events, alternatively use subsys_glob:event_glob to filter by tracepoint subsystems such as sched, block, etc.
- 5. If none of the above is matched, it will apply the supplied glob to all events, printing the ones that match.
perf-stat(1), perf-top(1), perf-record(1), m[blue]Intel® 64 and IA-32 Architectures Software Developercqs Manual Volume 3B: System Programming Guidem, m[blue]AMD64 Architecture Programmercqs Manual Volume 2: System Programmingm
- Intel® 64 and IA-32 Architectures Software Developercqs Manual Volume 3B: System Programming Guide
AMD64 Architecture Programmercqs Manual Volume 2: System Programming
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Time: 05:29:07 GMT, December 24, 2015